1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device for nonvolatilely writing data in accordance with application of a voltage to a variable resistive element.
2. Description of the Related Art
In recent years, attention has been focused on a nonvolatile memory comprising memory cells each containing a variable resistive element, which are connected at intersections of word lines and bit lines and arranged in matrix.
Known examples of the nonvolatile memory of such the type include: a PRAM (Phase-Change Random Access Memory) that uses a chalcogenide element as the variable resistive element; a ReRAM (Resistance Random Access memory) that uses a transition metal oxide element; and a CBRAM (Conductive Bridging RAM) that changes the resistance by precipitating metal cations to form a bridge between electrodes and ionizing the precipitated metal to destruct the bridge. These variable resistive memories are characterized in that the variation in resistance is stored as information.
The PCRAM utilizes the shape, such as the magnitude and the width, of a current/voltage pulse applied to the chalcogenide element to control the process from heating to cooling, thereby causing a phase change between the crystalline state and the amorphous state to control the resistance of the element (see Patent Document 1: JP 2002-541613T).
The ReRAM includes the bipolar type and the unipolar type. In the case of the bipolar type, the direction of the current/voltage pulse applied to the transition metal oxide element is used to control the resistance of the element. On the other hand, in the case of the unipolar type, the magnitude and the width of the current/voltage pulse applied to the transition metal oxide element are used to control the resistance of the element.
In the case of the ReRAM of the unipolar type, data can be programmed in a variable resistive memory by applying a program voltage of around 4.0 V to the variable resistive element (actually about 6V including a voltage drop of diode) for around 10 ns, thereby changing the variable resistive element from a high-resistance state to a low-resistance state. This state change is referred to as “program” or “set”. When an erase voltage of around 0.7 V is applied to the data-programmed variable resistive element (actually about 2.2 V including a voltage drop of diode) and a flow of current of 1-10 uA is applied for 200 ns to 1 us, the variable resistive element is changed from the low-resistance state to the high-resistance state. This state change is referred to as “erase” or “reset”.
The memory cell has a high-resistance state as a stable state (reset state or erase state), and a low-resistance state as a set state or program state, for example. In a case of two-bit per cell, data is written by a set operation of applying a set pulse to only the cell to be programmed among the memory cells in the reset state, for example. In an erase operation, a reset pulse is applied, irrespective of the cell state (set state or reset state).
A read operation of the memory cell involves applying a voltage of 0.4V (actually about 1.9V including a voltage drop of diode) to a variable resistive element and monitoring a current flowing via the variable resistive element. Thereby, the data stored in the variable resistive element is read by detecting whether the variable resistive element is in the low-resistance state or the high-resistance state.
A certain processing time is required for performing the set operation, reset operation or read operation for a memory cell array provided on a semiconductor substrate. Particularly, the reset operation requires a longer voltage application time and takes a longer time for processing than the set operation. In a sequence control of performing the other operation (e.g., set operation) for the other memory cell array after completing the operation (e.g., reset operation) for one memory cell array, the succeeding operation waits until the preceding operation is ended.
A flash memory having a plurality of cores, each being a set of blocks in units of data erase, and capable of simultaneously performing the data write or erase operation in one core and the data read operation in the other core was described in patent application 2. However, in patent application 2, since a control circuit is provided for each core, the operation for the other memory block cannot be started until the operation for one memory block is ended in a plurality of memory blocks within the core. Also, since the memory block is a unit of data erase, the simultaneous operation is not allowed for each memory cell array within the memory block. Therefore, the time required for the operation of the semiconductor memory device is longer, whereby the processing capacity can not be increased.